Consumer electronic equipment has been further advanced in the recent trend of high-speed and low power consumption for microcomputers etc., and semiconductor elements for semiconductor devices used in such computers are also miniaturized rapidly. Accordingly, unwanted radiation, that is, electromagnetic wave noise generated from electronic equipment, has been a serious problem. As a measure to decrease such unwanted radiation, a technique to build capacitor elements with large capacity in semiconductor integrated circuit devices and the like has attracted attention. Such capacitor elements have capacitor dielectric films of dielectric with high dielectric constant (hereinafter, high dielectric). With the trend of high integration of dynamic RAM, a technique to use high dielectric materials for a capacitor dielectric film instead of conventional silicon oxides or nitrides is widely researched. Moreover, research and development concerning ferroelectric films having spontaneous polarization property has been popular in order to practically apply a non-volatile RAM that enables writing and reading with lower working voltage and higher speed compared to conventional devices.
A method for manufacturing a conventional semiconductor device is explained below referring to FIGS. 4A to 4D. FIGS. 4A-4D are cross-sectional views showing the process of manufacturing a conventional semiconductor device.
As shown in FIG. 4A, a separation oxide film 2, a diffusion area 3 to be a source and drain for a transistor, a gate electrode 4 comprising polysilicon, and an interlayer capacitor dielectric film 5 comprising a silicon oxide film etc., are formed on a silicon substrate 1, on which a lower electrode 6a comprising a multilayer of titanium and platinum, a capacitor dielectric film 6b comprising a ferroelectric film such as PZT (lead (Pb) zirconate titanate) and SrBi.sub.2 Ta.sub.2 O.sub.9 and the like are formed throughout. Then, each layer is etched to have a desirable pattern by dry-etching such as ion milling using argon ions, so that a capacitor element 6 is formed. Next, as shown in FIG. 4B, an interlayer dielectric film 7 for the capacitor element is formed on the whole surface, and also formed contact holes 8 to reach a diffusion area 3, lower electrode 6a and upper electrode 6c. Next, as shown in FIG. 4C, a first wiring layer 9 and a second wiring layer 10 are formed on the whole surface. The first wiring layer is a diffusion barrier layer to restrain eutectic reaction between platinum used for the electrode material of the capacitor element and aluminum used for the second wiring layer, and comprises titanium nitride. Subsequently, the first wiring layer 9 and the second wiring layer 10 are etched selectively and then, annealed in a nitrogen atmosphere at 450.degree. C. to relieve the stress applied to the capacitor element.
In the semiconductor device manufactured in the conventional method, however, the stress provided to the capacitor element is still great even by annealing after forming the first and second wiring layers, and thus, the leakage current of the capacitor element increases and the dielectric breakdown volume is lowered.